Assembly Language
A MIPS based computer has a direct mapped cache. The address received by the cache is divided into the following fields: Index 9-5 Tag 31-10 Offset 4-0 a) 2.5 Pts] What is the cache block size (in words)? And how many lines does this cache have? b) [2.5 Pts] What is the ratio of the overhead bits w.r.t the total number of bits in the cache? c) [5 Pts] Starting from power on, the
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