(Solved) : Help Alu Done Vhdl Instructions 24 Bits 0 23 Picture Missing 22 Complete 3 Stage Pipelined Q32276093 . . . .

Help with the ALU, can it be done in vhdl. The instructions are24 bits, so 0-23. The picture is missing 22.

The complete 3-stage pipelined design is to be developed in astructural way with several modules operating simultaneously. Eachmodule represents a pipelined stage with its interstage register.The major units inside those stages modules are describedbelow.

Multimedia ALU

The ALU must be implemented as behavioral model in VHDLor continuous assignment (dataflow)