Help with the ALU, can it be done in vhdl.
The complete 3-stage pipelined design is to be developed in astructural way with several modules operating simultaneously. Eachmodule represents a pipelined stage with its interstage register.The major units inside those stages modules are describedbelow.
Multimedia ALU
The ALU must be implemented as behavioral model in VHDLor continuous assignment (dataflow) models inVerilog.
Register file
The register file has 32 128-bit registers. On any cycle, therecan
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