(Solved) : General Statement Implement Function F B C D Sum 0 1 7 13 15 Don T Cares 2 6 8 9 10 Using Q29139143 . . . .

General Statement: Implement functionF(A,B,C,D) = Sum(0,1,7,13,15) +Don’tCares(2,6,8,9,10) by only using two-levellogic. Thus, you are to draw the circuit using theXilinx ISE Schematic Editor, and then simulate itusing the Xilinx ISE Simulator. You are to get aprintout of the Simulation results (i.e. the timing diagram).

Also you are to provie:

1. Verilog test bench code

Once your design is verified using the Xilinx simulator, you areto get (1) a printout of the actual circuit from the SchematicEditor and (2) a printout of the simulation waveforms.

// Initialize Inputs

   integer i=0;

       initial begin

D = 0;

C = 0;

                       B = 0;

                       A = 0;

                       #16 $display (“starting test”);

                       for