
6. Design a negative-level sensitive D-Latch at the transistor level. 7. Design a positive-edge triggered D-FF at the transistor level. Show transcribed image text
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6. Design a negative-level sensitive D-Latch at the transistor level. 7. Design a positive-edge triggered D-FF at the transistor level. Show transcribed image text
An answer will be send to you shortly. . . . .