Assume you are a design engineer and are asked to design acircuit that takes as input a serial bit steam (read the input dataat the rising edge of the clock signal) and outputs a ‘1’ wheneverthe sequence “1011” occurs. This circuit should also have anasynchronous reset signal. Therefore, your input signals shouldinclude data_in, clk, reset and your output signal(s) shouldinclude data_out.
For instance, the following gives an example of input andoutputs:
data_in: 0110111011010110010110
data_out: 0000010001000010000010
(1) Draw both the Mealy and Moore type state transitiondiagrams
(2) Write VHDL code to implement your Mealy design
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