Pages 5 & 6: From Quarter 2: Instruction SetAnalysis and CPU Architecture 15 points in two parts
We need to develop an instruction set, formats, and CPUarchitecture to support the following operations:
R3 <—- R1 OP R2: 32 instructions
R1 <—- R1 OP R2: 32 instructions
MEM <—- R1: 32 instructions
R2 <—- R1 OP MEM: 16 instructions
MEM <—- R1 OP R2: 16 instructions
The machine has 8 general purpose registers, each 16 bits insize. Memory is accessed by a base plus displacement of 16bits.
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