NOTE- DON’T BE COPY_PASTE FROM GOOGLE ; I ALREADY FINDIT BUT I CAN’T BE ABLE TO UNDERSTNAD .
PLEASE PROVIDE OWN BETTER EXPLANATIONS / NOT CHEAT.
Q. A processor uses 2-level page tables for virtualto physical address translation. Page tables for both levels arestored in the main memory. Virtual and physical addresses are both32 bits wide. The memory is byte addressable. For virtual tophysical address translation, the 8 most significant bits of thevirtual address are used as index into the first level page tablewhile the next 12 bits are used as index into the second level pagetable. The 12 least significant bits of
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