A microprocessor has a memory write timing as shown in Figure3.18. Its manufacturer
specifies that the width of the Write signal can be determinedby T – 50, where T is the
clock period in ns.
a. What width should we expect for the Write signal if busclocking rate is 5 MHz?
b. The data sheet for the microprocessor specifies that the dataremain valid for 20 ns
after the falling edge of the Write signal. What is the totalduration of valid data
presentation to memory?
c. How many wait states should we insert if memory requiresvalid data presentation for
at least 190 ns?
Clock
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