Below is a list of 32-bit memory address references, given asword addresses:
3, 180, 43, 2, 191, 88, 14, 111, 181, 44, 111, 253
You are asked to optimize a cache design for the givenreferences. There are three direct-mapped cache designs possible,all with a total of 8 words of data: C1 has 1-word blocks, C2 has2-word blocks, and C3 has 4-word blocks. In terms of miss rate,which cache design is the best? If the miss stall time is 25cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles,and C3 takes 5 cycles, which is the best cache design?
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