Let us assume a typical pipeline, with the following fivestages:
1. Instruction fetch cycle (IF).
2. Instruction decode/Register fetch cycle (ID).
3. Execution/Effective address cycle (EX).
4. Memory access (MEM).
5. Write- back cycle (WB).
Assume that each stage would take just one clock cycle tocomplete its task, compite CPI with pipelining and withoutpipelining.
TYPE (or Catagory)FREQUENCYLATENCYload10%5 cyclestore15%5 cyclecomparison15%5 cycleadd55%5 cycledivide5%5 cycle
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