Ingress and Egress Nodes
Suppose you are given an acyclic directed graph G thatrepresents a combinational circuit C, where each node issub-circuit (e.g., AND gate, OR gate, NOT gate, 2:1 multiplexer,4:1 demultiplexer, 4-bit adder, etc) and directed edges are wires.Each node and edge has a nonnegative weight value that representsthe propagation delay of the circuit or wire. The propagation delayfor a node v is denoted by w(v), and the propagation delay for anedge (wire) connecting the output of circuit u to the input ofcircuit v is denoted by w(u,v).
Note that circuit C will have inputs and outputs. As shown inthe figure
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