Hi, may I know the solutions for Question 1) a, b, and c
Thank you.
Your help much appreciated.
![Pipeline In a 5-stage pipelined architecture, the following piece of code is executed t5,4Stl) $t3, $t5, $t4 add or and $t2, 24 (St3) SW add a. ldentify all data dependencies in the above code 3 marks] Assume that the CPU cannot detect any hazards and it does not have a forwarding unit either. Use nop instructions and insert it manually in the code so that it will run correctly [2 marks] The CPU is now equipped with Hazard Detection Unit that is able to stall pipelines and insert bubbles in the pipeline. Show the execution of the code for the clock cycles in the table in APPENDIX I. Use notation IF ID EX -instruction fetch instruction decode - execution - memory - Write back WB 4 marks]](../../../media.cheggcdn.com/media/703/7031ec7a-09f0-4921-84dc-4d0953388070/phpIBRrlI.png)
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Hi, may I know the solutions for Question 1) a, b, and c
Thank you.
Your help much appreciated.
![Pipeline In a 5-stage pipelined architecture, the following piece of code is executed t5,4Stl) $t3, $t5, $t4 add or and $t2, 24 (St3) SW add a. ldentify all data dependencies in the above code 3 marks] Assume that the CPU cannot detect any hazards and it does not have a forwarding unit either. Use nop instructions and insert it manually in the code so that it will run correctly [2 marks] The CPU is now equipped with Hazard Detection Unit that is able to stall pipelines and insert bubbles in the pipeline. Show the execution of the code for the clock cycles in the table in APPENDIX I. Use notation IF ID EX -instruction fetch instruction decode - execution - memory - Write back WB 4 marks]](../../../media.cheggcdn.com/media/703/7031ec7a-09f0-4921-84dc-4d0953388070/phpIBRrlI.png)
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