examine the verilog module provided on the course website forthis experiment and sketch a schematic of the logic that itrealizes. hint: this program realizes a bounceless switch, two srlatches with enables, and a d flip-flip (corresponding to always@(posedge —) block ).
CODE BELOW
module lab8(CLKIN, CS, RS, SS, CM, RM, SM, D, NC, NO,BQ, QM, QM_N, QS, QS_N, QFF);//INPUTSinput CLKIN/*synthesis loc=”1″*/;input CS /*synthesis loc=”2″*/;input RS /*synthesis loc=”3″*/;input SS /*synthesis loc=”4″*/;input CM /*synthesis loc=”5″*/;input RM
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