Develop a model to capture the performance penalty differencesfrom an I-cache miss and a D-cache miss for this pipeline (seepicture). Assume, that the ideal CPI of the machine is onlyaffected by these two types of cache misses, so you can ignorebranch mis-prediction, exception, TLB misses, and so forth. Developa model reflecting the functional characteristics of anOut-of-Order machine. You may assume:
- The issue width of the machine is I.
- The Re-order buffer size of the machine is R.
- The Instruction Window of the machine is W.
- Miss-penalty cycles of an I-cache miss and D-cache miss areidentical –
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