(Solved) : Design 3 Bit Cpa Adder Follows First Create Structural Model 1 Bit Full Adder Refer Homewo Q36331683 . . . .

Design a 3-bit CPA adder as follows:

First, create a structural model of a 1-bit Full Adder (refer tohomework 4) and instantiate it 3 times inside your 3-bit CPA moduleand make the necessary wire connections. To instantiate the Fulladder module, you need to add an `include line ontop of your CPA Verilog module.

Your module ports (inputs and outputs), should be as follow:

`include full_adder.v

module adder_3bits

(

input [2:0] a, b,

input cin,

output [2:0] sum,

output co

);

2. Create a test bench to test the followingcases:

a = 3’b001 b = 3’b001 cin = 1’b0

a = 3’b011 b = 3’b010 cin = 1’b1

a = 3’b011 b = 3’b100 cin