![containing destination Opcode of destination forwarded ifequal then Repister-egister ALU, Top ALU EMIRIrd] Repister eepister ALU Bonm ALU EXMEM.IRIrd] Register-egister ALU Bottom ALUMMne.:R “ Regiveregiser ALU Bomom ALU EX/MEM.IRIrt) Consider the two short MIPS instruction sequences below ADD R2, R3, R4 STORE R2.0R1) ADDI R2, R3, #100 STORE R2, 0(R1) Are the comparisons in the table above able to handle a forwarding path to the ALU inputs required for these instruction sequences? If so, indicate which row(s) are the relevant ones. If not, add the row(s) necessary](https://d2vlcm61l7u1fs.cloudfront.net/media%2Ffdd%2Ffdd8f255-2cb1-4958-b865-1f159279f550%2FphpOeVGHF.png)
containing destination Opcode of destination forwarded ifequal then Repister-egister ALU,
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![containing destination Opcode of destination forwarded ifequal then Repister-egister ALU, Top ALU EMIRIrd] Repister eepister ALU Bonm ALU EXMEM.IRIrd] Register-egister ALU Bottom ALUMMne.:R “ Regiveregiser ALU Bomom ALU EX/MEM.IRIrt) Consider the two short MIPS instruction sequences below ADD R2, R3, R4 STORE R2.0R1) ADDI R2, R3, #100 STORE R2, 0(R1) Are the comparisons in the table above able to handle a forwarding path to the ALU inputs required for these instruction sequences? If so, indicate which row(s) are the relevant ones. If not, add the row(s) necessary](https://d2vlcm61l7u1fs.cloudfront.net/media%2Ffdd%2Ffdd8f255-2cb1-4958-b865-1f159279f550%2FphpOeVGHF.png)
containing destination Opcode of destination forwarded ifequal then Repister-egister ALU,
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