Consider a pipeline with forwarding, hazard detection, and 1delay slot for branches. The pipeline is the typical 5-stage IF,ID, EX, MEM, WB MIPS design.
For the below code, complete the pipeline diagram below(instructions on the left, cycles on top) for the code. Insert thecharacters IF, ID, EX, MEM, WB for each instruction in theboxes.
Assume that there two levels of bypassing, that the second halfof the decode stage performs a read of source registers, and thatthe first half of the write-back stage writes to the registerfile.
I1 and R1 = R9 & R1I2 lw R1, 100 (R3)I3 add R2 = R2 + R1I4
OR
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