Consider the code below.]
Loop:
fld f0, 0(x1)
fmul.d f4, f0, f2
fsd f4, 0(x1)
fsub.d f4, f10, f14
addi x1, x1, 8
bne x1, x2, Loop // branches if x1 /= x2
Assume the following latencies: (a) fld/fsd: 1 cycle (b) fsub.d:2 cycles (c) addi/bne: 1 cycle (d) fmul.d: 6 cycles
Execute the code using hardware-based speculation andmultiple issue. Show theexecution by reusing the table shown in Figure 3.24 below. Assumeissue width of 2. (a) Show the status of associated reservationstations, reorder buffer, and registers after issuing the first twoinstructions in cycle 1.
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