Assume the following delays for an single-cycle datapath :
Memory read/write: 10ns,
Register file read/write: 3ns
ALU operations: 5ns ,
All other components have negligible delay.
We assume a benchmark with the following distribution ofinstructions: 20% add, 30% lw,
30% beq, 20% sw. Determine the execution times for one instance ofeach of the 4
instructions listed, and then identify the minimum clock cycle forthis benchmark.
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