
5) Consider the following Verilog code if (A) y- 1 else if (B) y-2 else if (C) y 3 else if (D) y 4 else у 0; Show what would most likely be synthesized. 6) Rewrite the code from the previous problem as a case statement. Show what would be synthesized if the parallel case synthesis directive is used. Show transcribed image text
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