
4. Consider a pipelined machine operating at 200 Mhz, with the following program execution characteristics Instruction class CPI Frequency 45% 25% 20% 7% 3% R-Type Immediate 4 lw 4 SW beq The designers decided to add a new addressing mode wherein registers can be automatically incremented by 4. Therefore a sequence such as code block 1 below can be replaced by the instruction shown in code block 2. We have 30% of the lw instructions affected in this manner. Assuming that
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