2) (8 pts) Suppose you are architecting a 32-bit system. The chip designers have a limited your cache size to 4MB of SRAM. You have chosen to use a 4-way set associative cache with 32 bytes per cache block. What is the format of a memory address as seen by the cache? Hint: Be determining the address format, you must convert everything to bytes.) e this architecture is byte-addressable, and the number of addresses
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