1. Use structural-style Verilog code to design a module for multiplying any 3-bit number A 2:0 with any 4-bit number Bi3:0 2. For the multiplier module, create a 8e1 command to show the decima values of Stime, A[2:0] (input), BI3:0 nput), and C[6:0 output). To ensure that the self-checking mechanism is functiona, use force command to simulate: (a) one stuck-at-0 fault at input Blol when B / 1111) ald A = [111, and (b) one
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