1. a) Consider the following Verilog code. It results in a warning. Explain the warning in your own words and suggest how can you eliminate it. module myCircuit (input [1:0] in, output reg [3:01 out) always e (in) begin case (in) 2″b00: out = 4 ‘b0000; 2’b01: out4’b1111 endcase end endmodule b) Write a Verilog module to implement the circuit outlined by the circuit shown in the Figure 6. The circuit has one input
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