
B.1 [0/1010/151<B.1 > You are trying to appreciate how important the principle of locality is in justify ing the use of a cache memory, so you experiment with a com- puter having an L1 data cache and a main memory (you exclusively focus on data accesses). The latencies in CPU cycles) of the different kinds of accesses are as follows: cache hit, 1 cycle; cache miss, 110cycles; main memory access with cache disabled, 105
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