(Solved) : Create Code Vhdl Project Design First First Fifo Register Storage Queue Total 16 Fifo Orde Q32161521 . . . .

Create a code in VHDL

For this project you will design a First In First Out (FIFO)Register storage queue with a total of 16 FIFO-ordered Four-BitRegisters and accessible through two independent interfaces orports.

The Model should be able to accept Write_H Commands for datapresented at it’s Data_In_H (3:0) port until the FIFO is Full whichshould be indicated by asserting a Full_H out status signal.

The model should be able to accept Read_H Commands with datashowing at the Data_Out_H (3:0) port until the FIFO is Empty whichshould be indicated by asserting an Empty_H out signal.

Considering that this FIFO might be accessed by separateentities on